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Quarantech Tuesday: FREE Technical Webinar Series

We are excited to announce a new technical webinar series, Quarantech Tuesday! The webinar episodes, co-hosted by BlueRing Stencils and FCT Solder have SMT Experts on the show to share their knowledge and answer any questions you may have in real-time. Tune in every other week as we discuss common assembly defects, yield issues, and simple solutions to enhance every assembly process. 

Don’t miss out on the first webinar!
WHERE: Zoom
WHEN: October 6, 2020
TIME: 2:00 PM EST
TOPIC:  How to Fill the Void – Mitigation of Voiding For Bottom Terminated Components
SIGN UP - SPACE IS LIMITED!
Join us as BlueRing Stencils’ Greg Smith and Tony Lentz from FCT Solder discuss their 2020 APEX paper. 
 
ABSTRACT Voiding in solder joints has been studied extensively, and the effects of many variables compared and contrasted with respect to voiding performance. Solder paste flux, solder powder size, stencil design, circuit board design, via-in-pad design, surface finish, component size, reflow profile, vacuum reflow, nitrogen reflow and other parameters have been varied and voiding quantified for each. The results show some differences in voiding performance with respect to most of these variables but these variables are not independent of each other. Voiding in solder joints is a complex issue that often requires multiple approaches to reduce voiding below required limits. This paper focuses on solutions to voiding for commonly used bottom terminated components (BTCs). When voiding is an issue, it is often not possible to change the solder paste or circuit board design due to end user requirements and time constraints. It is much easier to change the stencil design and the reflow profile in an effort to reduce voiding, and this can be done in a timely manner. Stencil design and reflow profile can be used to minimize voiding for BTCs like Quad Flat No Lead (QFN) components. Optimization of the window pane size and web width can help with voiding. Changing the volume of solder paste on the I/O perimeter pads of QFNs also has an effect on voiding. Use of linear ramp-to-spike (RTS) reflow profiles reduces voiding with some solder pastes, while ramp-soak-spike (RSS) profiles work better for other solder pastes. Stencil design and reflow profile were optimized for a variety of QFN components in order to minimize voiding. The results of this testing were quantified, summarized and recommendations given for ideal voiding performance.
 

LEARN MORE ABOUT OUR PRESENTERS:

Find Tony Lentz on LinkedIn
Find Greg Smith on LinkedIn 

Look for more information about future topics, including:

 –  Unique printing technologies
 –  High reliability alloys
 –  Tooling and fixture advancements
 –  Stress-free depaneling solutions
 –  …and MORE!!!

Get the next webinar on your calendar!
Root Cause Workshop – Stencil Design for SMT Component Thermal Lands on October 20th

PRE-REGISTER TODAY
COVID-19 Update Keep Up with Industry Trends! Register for Quarantech Tuesdays

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